Test-response comparison circuit and scan data transfer scheme in a DFT architecture for micro LED based display panels
US10891884B1 · kind B1 · utility
2Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2019 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Apr 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Design-for-test (DFT) architectures, and methods of testing an array of chips, which may be identical, are described. In an embodiment, a comparison circuit includes a plurality of comparators to compare scan-data out (SDO) data streams with an expected data stream and transmit a compared data stream that is indicated of whether or not an error exists in any of the SDO data streams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.