Soft erase and programming of nonvolatile memory
US10892025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2019 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Jun 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile storage apparatus includes a plurality of non-volatile memory cells and control circuitry. The control circuitry is configured to apply one or more soft erase pulses to the plurality of non-volatile memory cells to reduce threshold voltages of the plurality of non-volatile memory cells from initial levels corresponding to programmed data to intermediate levels below the initial levels and above an erased level. The control circuitry is configured to apply one or more soft programming pulse to increase threshold voltages of the plurality of non-volatile memory cells from the intermediate levels to final levels corresponding to the programmed data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.