Patent · US Active

Defect-tolerant layout and packaging for GaN power devices

US10892254B2 · kind B2 · utility

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8Claims

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Inventors

Zhanming Li · West Vancouver, CA
Guanhou Luo · Foshan, CN
Yue Fu · Coquitlam, CA
Wai Tung Ng · Plano, US
Yan-Fei Liu · Kingston, CA

Key dates

Filing date	May 11, 2019
Grant date	Jan 12, 2021
Priority date	—
Expiry date	May 11, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15313
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Use of gallium nitride (GaN) semiconductor material for power devices is challenging due to low yield caused by high defect density on the wafer. Device layout on the wafer, chip probing, and device packaging increase the yield of large area power devices. Device dies containing a plurality of lower-power sub-devices are used to achieve high power ratings, by connecting only functional sub-devices together in the package, while being tolerant of defective sub-devices by selectively excluding the defective sub-devices. The packages and methods are particularly relevant to GaN power switching devices such as high electron mobility transistors (GaN HEMT).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.