ESD-robust stacked driver
US10892258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2019 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Aug 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated “pull-down” driver circuit (210) is formed with a combination device consisting of an output driver transistor (N1) electrically coupled between a current source circuit (Ns) and the conductive pad, and an ESD bypass transistor (N3) electrically coupled in series with the output driver transistor, where one or more conductive interconnect layers connect the ESD bypass transistor in parallel with the current source circuit so that the ESD bypass transistor is in an off-state during normal operation and is activated to form a parasitic bipolar junction transistor with the output driver transistor to conduct ESD current between a first power supply conductor and the conductive pad during ESD events, and where a complementary integrated “pull-up” driver circuit may be formed with three corresponding PMOS transistors (P1, PS, P3) connected as shown between a second power supply conductor and the conductive pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.