Virtual inductors using ferroelectric capacitance and the fabrication method thereof
US10892728B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Feb 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2001/0085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Devices, system and methods a circuit, including a resistor, a normal capacitor and a ferroelectric capacitor connected in series. An input terminal to provide an input voltage across the circuit. An output terminal to deliver an output voltage taken across the normal capacitor. The circuit comprises a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer. The first buffer layer contacts a portion of a first metal layer and first metal layer extends beyond the first buffer layer. A dielectric layer sandwiched between a second metal layer and a third metal layer. Such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer. Wherein the ferroelectric capacitor is formed by the first metal layer. The ferroelectric layer sandwiched between the first buffer layer and the second buffer layer, and the second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.