Communication receiver interface for current loop circuit
US10892925B2 · kind B2 · utility
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1References
22Claims
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Key dates
| Filing date | Nov 16, 2018 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Nov 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017545
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for an integrated circuit, current loop interface that can receive and extract a high-frequency digital communication signal from a low-frequency analog current signal using a complex impedance circuit. The complex impedance circuit can allow for low input impedance at the lower frequencies of the analog current signal and high input impedance at the higher frequencies of the digital communication signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.