Integrated circuit device including gate spacer structure
US10896967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2019 |
| Grant date | Jan 19, 2021 |
| Priority date | — |
| Expiry date | May 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/666
Abstract
An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.