Patent · US Active

Memory allocation in multi-core processors

US10901639B2 · kind B2 · utility

1Cited by

5References

13Claims

0Family size

Assignee

SAP SE · DE

Inventors

Daniel Booss · Angelbachtal, DE
Robert Kettler · Heidelberg, DE
Mehul Wagle · Pune, IN
Harshada Khandekar · Pune, IN
Ivan Schreter · Malsch, DE

Key dates

Filing date	Feb 8, 2017
Grant date	Jan 26, 2021
Priority date	—
Expiry date	Oct 24, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/6046
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system for allocating memory (e.g., heap) in multi-core processors is provided. In some implementations, the system performs operations comprising receiving, at a shared cache having a plurality of segments, a first data allocation including a plurality of data blocks, and allocating at least a first and second data block from the first allocation. First and second segments in the shared cache can each comprise a plurality of data slots (e.g., of equal length). Allocating the first and second data blocks can include storing the first data block in a data slot of the first segment and storing the second data block in a data slot of the second segment. The plurality of data slots which do not contain data may contain padding, and/or the data slots to which the first and second data blocks are allocated are not adjacent. Related systems, methods, and articles of manufacture are also described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.