Patent · US Active

Memory block erasure

US10901651B2 · kind B2 · utility

3Cited by

5References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Martin Bernhard Schmidt · Stuttgart, DE
Peter Altevogt · Ettlingen, DE
Wolfgang Gellerich · Eppelheim, DE
Juergen Pille · Stuttgart, DE

Key dates

Filing date	Jan 3, 2020
Grant date	Jan 26, 2021
Priority date	—
Expiry date	Jan 3, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments of memory block erasure are described herein. An aspect includes determining an initial word line set consisting of a single word line. Another aspect includes activating the single word line such that a first memory cell that is connected to the single word line is erased by the activation. Another aspect includes determining a first word line set consisting of the single word line and one additional word line, and wherein the one additional word line corresponds to a second memory cell have a maximum distance from the first memory cell along a bit line that includes the first memory cell and the second memory cell. Another aspect includes activating the first word line set, such that a respective memory cell that is connected to each of the first word line set is erased by the activation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.