Delay circuitry to hold up power to a mass storage device and method therefor
US10901851B2 · kind B2 · utility
1Cited by
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16Claims
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Assignee
Inventors
Key dates
| Filing date | May 4, 2018 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Jan 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay circuitry is configured to hold up power to a mass storage device after a power fault disables communication of the mass storage device with the host computer. The time delay is sufficient to allow saving of in-flight data from the storage device's volatile cache to the non-volatile media (of the storage device) and to update a metadata table in the non-volatile media.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.