Cached result use through quantum gate rewrite
US10901896B2 · kind B2 · utility
1Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2018 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Feb 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques facilitating cached result use through quantum gate rewrite are provided. In one example, a computer-implemented method comprises converting, by a device operatively coupled to a processor, an input quantum circuit to a normalized form, resulting in a normalized quantum circuit; detecting, by the device, a match between the normalized quantum circuit and a cached quantum circuit among a set of cached quantum circuits; and providing, by the device, a cached run result of the cached quantum circuit based on the detecting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.