Memory device
US10902905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2019 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line, and a second bias circuit inputting a second bias voltage to a selected bit line, a first switch element connected to the selected word line, and a second switch element connected between the first switch element and the first bias circuit; and a control logic configured to control the first and second switch elements, when a predetermined delay time elapses after the second bias voltage is input to the selected bit line. The control logic turns off the first switch element while the second switch element is turned on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.