Three-dimensional semiconductor memory device
US10903236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2019 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | Oct 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.