Computer system architecture
US10908975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2011 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Aug 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/44
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer system architecture including a first buffer, a second buffer, a sub-system and a CPU is provided. The sub-system carries out a first task to obtain first returned information, stores the first returned information in the first buffer and sets up a first occupancy flag to the first buffer. Next, the sub-system carries out a second task to obtain second returned information, stores the second returned information in the second buffer, and sets up a second occupancy flag to the second buffer. The CPU reads the first returned information and eliminates the first occupancy flag. After the second returned information is stored in the second buffer and the first occupancy flag is eliminated, the sub-system continuously carries out a third task to obtain third returned information, stores the third returned information in the first buffer, and sets up the first occupancy flag to the first buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.