Management of shared memory using asynchronous invalidation signals
US10909036B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2018 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Nov 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a shared memory accessible by a plurality of members of a shared memory system, and a processor operably coupled to the shared memory system. The processor is configured to receive a command from an exploiting member of the plurality of members, the command instructing an update to a piece of shared data, perform the update to the piece of shared data, and send an invalidation signal to each other member of the plurality of members. An invalidation signal sent to a respective member indicates that a local copy of the piece of data stored by the respective member is no longer valid, and each invalidation signal is sent asynchronously with respect to processing of the command. The processor is further configured to return the results of the command to the exploiting member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.