Optimization techniques for quantum computing device simulation
US10909286B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2018 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Apr 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer systems and methods are provided for increasing a rate of simulation for quantum computing devices. A quantum computing device includes a plurality of gates, each of which is coupled to one or more modes. In the provided computer systems and methods, a device definition and state information for the quantum computing device are received. The state information includes a plurality of input patterns, each of which indicates a number of input bosons that correspond to a respective mode of the quantum computing device, and an amplitude that corresponds to each input pattern. The device definition includes a plurality of sets of gate values that indicate modification by a respective gate of an input pattern probability. A first group of input patterns is generated for a first gate. The first group of input patterns includes a subset of the plurality of input patterns that meet grouping criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.