Ordering of patch selection in tessellation operations
US10909742B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Apr 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T17/205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling the order in which primitives generated during tessellation are output by the tessellation unit involves sub-dividing a patch, selecting one of the two sub-patches which are formed by the sub-division and tessellating that sub-patch until no further sub-division is possible before tessellating the other (non-selected) sub-patch. The method is recursively applied at each level of sub-division. Patches are output as primitives at the point in the method where they do not require any further sub-division. The selection of a sub-patch is made based on the values of one or more flags and any suitable tessellation method may be used to determine whether to sub-divide a patch. Methods of controlling the order in which vertices are output by the tessellation unit are also described and these may be used in combination with, or independently of, the method of controlling the primitive order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.