Patent · US Active

Integrated circuit package structure and package method

US10910288B2 · kind B2 · utility

0Cited by
8References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 14, 2019
Grant dateFeb 2, 2021
Priority date—
Expiry dateJun 14, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2224/97
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An integrated circuit package structure and a package method. The integrated circuit package structure includes: a semiconductor chip, an encapsulation layer covering the semiconductor chip, the encapsulation layer including a first encapsulation layer and a second encapsulation layer alternately stacked, a sum of a number of the first encapsulation layer and a number of the second encapsulation layer being at least 3; wherein a thermal expansion coefficient of one of the first encapsulation layer and the second encapsulation layer is positive, and a thermal expansion coefficient of the other of the first encapsulation layer and the second encapsulation layer is negative.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.