Semiconductor device
US10910363B2 · kind B2 · utility
0Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Mar 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.