Semiconductor device

US10910490B2 · kind B2 · utility

Assignees

• Kabushiki Kaisha Toshiba · JP
• Toshiba Electronic Devices & Storage Corporation · JP

Inventors

• Masahiko Kuraguchi · Yokohama, JP
• Yosuke Kajiwara · Yokohama, JP
• Aya Shindome · Yokohama, JP
• Hiroshi Ono · Setagaya, JP
• Daimotsu Kato · Tokyo, JP
• Akira Mukai · Kawasaki, JP
• Toshiki Hikosaka · Yokohama, JP
• Jumpei Tajima · Mitaka, JP

Key dates

• Filing date: Sep 10, 2019
• Grant date: Feb 2, 2021
• Expiry date: Sep 10, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85

Abstract

According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, a first layer including, and a first insulating layer. The first semiconductor region includes Alx1Ga1-x1N and includes first to fifth partial regions. The third partial region includes a first element including at least one selected from the group consisting of Mg, Zn, and C. The second semiconductor region includes Alx2Ga1-x2N and includes a sixth partial region and a seventh partial region. The third semiconductor region includes Alx3Ga1-x3N and includes an eighth partial region and a ninth partial region. The fourth semiconductor region includes Alx4Ga1-x4N and includes a tenth partial region and an eleventh partial region. The first layer includes AlyGa1-yN and includes a first portion provided between the third partial region and the third electrode. The first insulating layer includes a second portion provided between the first portion and the third electrode.