Fixed-width pulse generator
US10911035B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2020 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | May 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00234
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fixed-width pulse generator includes a metastability detector circuit, a delay signal generator, and a combinational logic circuit. The metastability detector circuit is configured to receive a trigger signal and generate state detection signals. The delay signal generator is configured to receive the state detection signals and the trigger signal, and delay the trigger signal by two different delay values to generate two different delayed signals. One of the delay values is based on the state detection signals. The combinational logic circuit is configured to receive the two delayed signals and an error signal, and generate a fixed-width pulse that remains constant over process, voltage, and temperature variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.