Dynamically adjustable CMOS circuit
US10911048B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 2020 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | May 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complementary metal-oxide semiconductor (CMOS) circuit comprises an inverter, a plurality of P-type metal-oxide semiconductor (PMOS) transistors, and a plurality of N-type metal-oxide semiconductor (NMOS) transistors. The inverter receives an input signal and drives one of the plurality of PMOS transistors or the plurality of NMOS transistors. The plurality of PMOS transistors generate a pull-up signal, change a beta ratio of the CMOS circuit, and change a first trip point of the CMOS circuit to a second trip point of the CMOS circuit based on the changed beta ratio. The plurality of NMOS transistors generate a pull-down signal, change the beta ratio, and change the second trip point of the CMOS circuit to a third trip point of the CMOS circuit based on the changed beta ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.