Multi-level signal clock and data recovery
US10911052B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Jul 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/3809
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.