Digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit
US10911054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2020 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Jun 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.