Method, apparatus and system for hierarchical network on chip routing
US10911261B2 · kind B2 · utility
1Cited by
47References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2016 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | May 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/4625
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a system on chip includes: a plurality of local networks having one or more local endpoints and a first router, where at least some of the one or more local endpoints of different local networks have non-unique port identifiers; at least one global network having one or more global endpoints and at least one second router, where the one or more global endpoints have unique port identifiers; and a plurality of transparent bridges to couple between one of the plurality of local networks and the at least one global network. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.