Systems and methods for on-chip filtering
US10911270B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Oct 1, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Oct 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03828
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described are systems and methods take advantage of properties of sinc filters that remove frequency components at specific integer multiples of a noise frequency. In various embodiments, sampling of multi-channel systems at sufficiently high rates allows for removal of unwanted signals and harmonics from multi-sample sequences. Advantageously, a multi-sample sequence scheduling scheme eliminates the need for noise filtering one channel at a time at each channel's own sampling rate using a separate filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.