Test circuit and semiconductor device
US10914783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2019 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Mar 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/32
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.