Gate driver on array circuit and driving method thereof, and display device
US10916178B2 · kind B2 · utility
1Cited by
2References
11Claims
0Family size
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Key dates
| Filing date | Oct 19, 2017 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Oct 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A Gate Driver on Array circuit and a driving method thereof, and a display device. The Gate Driver on Array circuit includes at least one group of shift registers, each group of shift registers includes a plurality of shift registers in cascade, the plurality of shift registers including a first shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with an initializing terminal connected to an output terminal of the first shift register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.