Code compilation for scaling accelerators
US10922063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2018 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Feb 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system comprises a work accelerator, a gateway the transfer of data to the accelerator from external storage, the accelerator executes a first compiled code sequence to perform computations on data transferred to the accelerator from the gateway. The first compiled code sequence comprises a synchronisation instruction indicating a barrier between a compute phase in which the compute instructions are executed and an exchange phase, wherein execution of the synchronisation instruction causes an indication of a pre-compiled data exchange synchronisation point to be transferred to the gateway. The gateway comprises a streaming engine storing a second compiled code sequence in the form of a set of data transfer instructions executable by the streaming engine to perform data transfer operations to stream data through the gateway in the exchange phase, wherein the first and second compiled code sequences are generated as a related set at compile time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.