Host processor configured with instruction set comprising resilient data move instructions
US10922078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a host processor and at least one storage device coupled to the host processor. The host processor is configured to execute instructions of an instruction set, the instruction set comprising a first move instruction for moving data identified by at least one operand of the first move instruction into each of multiple distinct storage locations. The host processor, in executing the first move instruction, is configured to store the data in a first one of the storage locations identified by one or more additional operands of the first move instruction, and to store the data in a second one of the storage locations identified based at least in part on the first storage location. The instruction set in some embodiments further comprises a second move instruction for moving the data from the multiple distinct storage locations to another storage location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.