Reduction operations in data processors that include a plurality of execution lanes operable to execute programs for threads of a thread group in parallel
US10922086B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To perform a reduction operation to combine data values for threads in a thread group using a data processor, the data processor performs combining steps that each combine the stored combined data value result of a previous combining operation for a thread with the combined data value result of the previous combining operation for a selected another execution lane that has not yet contributed to the stored combined data value result for the thread. The data processor selects as the another execution lane of the execution processing circuitry that has not yet contributed to the combined data value result for the thread, an execution lane from a group of execution lanes whose values have been combined in the previous combining step and that have not yet contributed to the combined data value result for the thread, and having a particular relative position in the group of execution lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.