Processor instruction support to defeat side-channel attacks

US10922088B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Fangfei Liu · Hillsboro, US
• Bin Xing · Hillsboro, US
• Michael Steiner · Windom, US
• Mona Vij · Hillsboro, US
• Carlos V. Rozas · Portland, US
• Francis X. McKeen · Portland, US
• Meltem Ozsoy · Hillsboro, US
• Matthew Fernandez · Portland, US
• Krystof C. Zmudzinski · Forest Grove, US
• Mark W. Shanahan · Raleigh, US

Key dates

• Filing date: Jun 29, 2018
• Grant date: Feb 16, 2021
• Expiry date: Sep 3, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2221/034
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.