Intelligent layout of composite data structures in tiered storage
US10922287B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Jun 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the subject technology relate to ways to determine the optimal storage of data structures in a hierarchy of memory types. In some aspects, a process of the technology can include steps for determining a latency cost for each of a plurality of fields in an object, identifying at least one field having a latency cost that exceeds a predetermined threshold, and determining whether to store the at least one field to a first memory device or a second memory device based on the latency cost. Systems and machine-readable media are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.