Display gate drivers with dynamic and reduced voltage swing
US10923022B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Nov 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit in the chain of row driver circuits may include a master driver stage, a slave driver stage, and associated control circuitry configured to receive a clock signal and a pulse signal from a preceding row driver in the chain. The master driver stage may be biased using fixed nominal power supply voltages, whereas the slave driver stage may be biased using dynamically adjustable power supply voltages that are optionally reduced relative to that of the nominal power supply voltages. One or more of the master and slave driver stages may be a bootstrapping driver stage having a bootstrapping capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.