Gate driving circuit, method for implementing gate driving circuit, and method for driving gate driving circuit
US10923037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Apr 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0233
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The embodiments of the present disclosure disclose a gate driving circuit. The gate driving circuit includes at least one stage of shift register unit to be compensated, wherein a driving terminal of each stage of shift register unit to be compensated is connected to a gate line of a corresponding row of pixels to be compensated, and at least one stage of parasitics compensation circuit, wherein each stage of parasitics compensation circuit is connected in series between a power supply line and a driving terminal of a corresponding shift register unit to be compensated. Each stage of parasitics compensation circuit is configured to compensate a driving terminal of a corresponding shift register unit to be compensated for parasitic capacitance and/or parasitic resistance, so that respective stages of shift register units to be compensated have the same driving load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.