Gate driving circuit and driving method, array substrate, and display device
US10923063B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | May 31, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driving circuit includes 4n stages of shift register units, and n stages of inversion units. One of the inversion units is disposed between every two groups of four adjacent stages of shift register units. A (n+1)th stage of the inversion units is disposed between two of the shift register units, and configured to output in inverted phases gate driving signals outputted by the two shift register units in a heavy-load screen stage, and output in positive phases gate driving signals outputted by the two shift register units in a normal screen stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.