Receiving circuit with offset voltage compensation
US10923074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Aug 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45318
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.