Array substrate with improvement reading speed, driving method and display device
US10923507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2018 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Jan 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0294
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An array substrate includes: a plurality of pixel units arranged in an array, selection lines, a reset circuit and readout circuits. Second terminals of transistors in pixel units belonging to a same column are connected to at least two of the read lines, so that a part of the pixel units are connected to a same read line, and another part of the pixel units are connected to the other one of the at least two of the read lines. For each column of the pixel units, each of the read lines is connected to one of the readout circuits corresponding to the column of the pixel units through a switching element; and for each column of the pixel units, each of the read lines is connected to the reset circuit through a switching element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.