High speed switching solid state relay circuit
US10924110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Aug 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M5/2937
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for high speed switching comprises receiving voltage inputs at a bridge rectifier, receiving a logic input signal at an optical isolator and generating an output signal from the optical isolator based on the logic input signal, and driving a gate of a field effect transistor (FET) via the output signal of the optical isolator, wherein a source of the FET is connected to a negative output of the bridge rectifier and a drain of the FET is connected to a positive output of the bridge rectifier through a load. The method further includes limiting current flowing to the gate of the FET through first and second resistors and first and second diodes connecting the voltage inputs to the gate of the FET and limiting voltage to the gate of the FET below a maximum voltage rating of the FET by a Zener diode connected to the gate of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.