No false lock DLL
US10924121B1 · kind B1 · utility
7Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2020 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Feb 11, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DLL circuit is disclosed. The DLL circuit includes a delay line, configured to receive a delay line input clock, and to generate a plurality of output clocks each having a phase based on a delay of the delay line. The DLL circuit also includes a control circuit, configured to selectively cause the delay line input clock to be equal to one of a DLL input clock and an inverted one of the output clocks of the delay line, and an edge combiner, configured to generate a DLL output clock based on the output clocks of the delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.