Phase error reduction in a receiver
US10924309B2 · kind B2 · utility
1Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2020 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Feb 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0024
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.