System and method for port reduction using multiple chassis link aggregation group for stacked devices
US10924435B2 · kind B2 · utility
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3References
18Claims
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Key dates
| Filing date | May 15, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Jun 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/253
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system includes servers that are connected in series, and a top of rack (TOR) switch having a first TOR switch port and a second TOR switch port that are connected to a first end and a second end, respectively, of the series connected servers. A multi chassis link aggregation group may be established on the first TOR switch port and the second TOR switch port to transform the series connected servers into a single logical channel. A highest media access control address is determined from the servers to represent the single logical channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.