Dynamic timer adjustment to improve performance and inhibit livelock conditions
US10929146B2 · kind B2 · utility
0Cited by
0References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2018 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Sep 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/86
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a semiconductor package apparatus may include technology to determine respective priority levels for one or more boot time events, determine an amount of execution time for the one or more boot time events, and automatically adjust a timer based on the amount of execution time and the priority levels for the one or more boot time events. Other embodiments are disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.