Processing system and heterogeneous processor acceleration method
US10929187B2 · kind B2 · utility
1Cited by
3References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 3, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Sep 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/548
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a core, at least one accelerator function unit (AFU) and an accelerator interface. The core is utilized to develop at least one task. The AFU is utilized to execute the task. The accelerator interface is arranged between the core and the AFU to receive an accelerator interface instruction transmitted by the processing core and instruct the AFU to execute the task according to the accelerator interface instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.