Memory controller including error correction code circuit, memory system including the memory controller, and operating method of the memory system
US10929223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | May 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is provided. The memory controller includes an error correction code (ECC) circuit configured to correct an error of a read codeword provided from a memory device, the ECC circuit including: a codeword combination generator configured to receive a first read codeword including a plurality of first read codeword bit values that are read from a first region of the memory device, generate a change codeword by changing values of one or more of the plurality of first read codeword bit values, and provide a codeword combination including the change codeword; and an ECC decoder including a plurality of ECC engines, wherein the ECC decoder is configured to perform ECC decoding in parallel on a plurality of codewords included in the codeword combination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.