Delayed error processing
US10929232B2 · kind B2 · utility
1Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2017 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jun 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.