Memory controlling device and computing device including the same
US10929291B2 · kind B2 · utility
1Cited by
0References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 23, 2018 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Nov 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controlling device of a computing device including a CPU, a memory, and a flash-based storage device is provided. The memory controlling device includes an address manager and an interface. The address manager aggregates a memory space of the memory and a storage space of the storage device into an expanded memory space, and handles a memory request for the expanded memory space from the CPU by using the memory space of the memory as a cache for the storage space of the storage device. The interface is used to access the memory and the storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.