Integrated circuit layout, structure, system, and methods
US10929588B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Feb 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating an IC layout diagram includes intersecting an active region with first and second gate regions to define locations of first and second anti-fuse structures, overlying the first gate region with a first conductive region to define a location of an electrical connection between the first conductive region and first gate region, and overlying the second gate region with a second conductive region to define a location of an electrical connection between the second conductive region and second gate region. The first and second conductive regions are aligned along a direction perpendicular to a direction along which the first and second gate regions extend, and at least one of intersecting the active region with the first gate region, intersecting the active region with the second gate region, overlying the first gate region, or overlying the second gate region is executed by a processor of a computer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.