Patent · US Active

Generating routing structure for clock network based on edge intersection detection

US10929589B1 · kind B1 · utility

0Cited by

18References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Dirk Meyer · Frankfurt, DE
Zhuo Li · Austin, US

Key dates

Filing date	Mar 19, 2020
Grant date	Feb 23, 2021
Priority date	—
Expiry date	Mar 19, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/394
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various embodiments provide for generating a routing structure for a clock network based on edge interaction detection, which can facilitate detection/consideration of overuse of routing resources to a balanced routing structure and which may be part of electronic design automation (EDA) of a circuit design. For example, some embodiments use an edge intersection check to detect overuse of routing resources within the routing structure for a clock network.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.