Metal gate structure cutting process
US10930564B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Aug 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.